Organizational behavior from the perspective of methodological isomorphism

Background: As an interdisciplinary research area at the interface of management theory, psychology, sociology, social anthropology, and cultural studies, organizational behavior (OB) still lacks a clear definition, whereas its status and scope have not been precisely determined. Some experts believe that the knowledge of all possible instances of OB and its constant improvement is the key to the proper calibration of management techniques, organizational dynamics, and more active staff. Others stress that OB has lost its significance and authority as an academic discipline. Purpose: The goal of the research is to develop an approach that complements and further develops concepts comprising OB theory as regards the identification of micro-, meso-, and macro-organizational behavior actors - individuals, groups, teams, the organization itself, and its external stakeholders. Study design/methodology/approach: The authors provide a solid framework for the principle of methodological isomorphism and its application to the indicators of OB - measures of organizational actions. Further, a possibility for the methodological integration of tools for managing the OB of all categories of actors is demonstrated. Findings/conclusions: An original definition of OB management is offered and justified. The focus is on the strategic context of efforts to improve OB. A strategy map used in OB management is provided as an illustration. It is concluded that the sustainable success of an organization heavily depends on how stakeholders (actors) perceive the efforts of the management to enhance working conditions and the organizational culture of the work environment, as well as to strengthen the market leadership of the organization. Limitations/future research: The research limitations lie in the scope of methodological challenges which need to be solved. New approaches to monitoring, analyzing, and evaluating the measurement results are going to be proposed and researched. The methodology and relevant calculations for perception indicators computation are going to be explored

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics

Exact parallel critical path fault tracing to speed-up fault simulation in sequential circuits

We propose a new method to speed up stuck-at fault simulation for sequential circuits. The method combines exact parallel critical path tracing of faults, used so far only for combinational circuits, with traditional fault simulation in sequential circuits. For that purpose, formulas are developed for classification of faults into two classes: the faults eligible for parallel critical path tracing, and the faults which have to be simulated over the global feedbacks in the circuit by traditional methods. Combining these two approaches in fault simulation ‒ the combinational and sequential simulation concepts ‒ allows dramatic speed-up of fault simulation in sequential circuits, which is demonstrated by experimental results

Fault Diagnosis in the BIST Environment Based on Bisection of Detected Faults

An optimized fault diagnosing procedure in Built-in Self-Test environment is proposed. Instead of bisection of patterns in pseudorandom test sequences, in the proposed bisection procedure the diagnostic information inherent in test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. The proposed method is compared with three known fault diagnosis methods: classical Binary Search, Doubling and Jumping. Experimental results have demonstrated the advantages of the proposed method compared to the known methods. 1

Fault Diagnosis in Integrated Circuits with BIST

This paper presents an optimized fault diagnosing procedure applicable in Built-in Self-Test environments. Instead of the known approach based on a simple bisection of patterns in pseudorandom test sequences, we propose a novel bisection procedure where the diagnostic weight of test patterns is taken into account. Another novelty is the sequential nature of the procedure which allows pruning the search space. Opposite to the classical approach which targets all failing patterns, in the proposed method not all failing patterns are needed to be fixed for diagnosis. This allows to tradeoff the speed of diagnosis with diagnostic resolution. The proposed method is compared with three known fault diagnosis methods: classical Binary Search, Doubling and Jumping. Experimental results demonstrate the advantages of the proposed method compared to the previous ones. 1

Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics